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2009 Microchip Technology Inc.

DS40044G-page 15

PIC16F627A/628A/648A

3.1

Clocking Scheme/Instruction

Cycle

The clock input (RA7/OSC1/CLKIN pin) is internally

divided by four to generate four non-overlapping

quadrature clocks namely Q1, Q2, Q3 and Q4.

Internally, the Program Counter (PC) is incremented

every Q1, the instruction is fetched from the program

memory and latched into the instruction register in Q4.

The instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow is shown in Figure 3-2.

3.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

OSC1

CLKOUT

PC + 1

PC + 2

Fetch INST (PC)

Execute INST (PC - 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

Internal

phase

clock

Note:

All instructions are single cycle except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL

SUB_1

Fetch 3

Execute 3

4. BSF

PORTA, 3

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

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